Layout Tips (130nm TSMC)

1) In order to start drawing the layout, we should have a ready to layout schematic of our design. It means there should be no GND, VDD or voltage or current sources in the schematic. Every node that is going to be connected to the pads should be a pin. It is better to use input-output and type signal. Be careful that using the words VDD or GND or VSS automatically change the type to power or ground. It is better to change it back to signal.
2) All the pin names should be just capital letters. (This is as I know just for TSMC)
3) Start the layout of this schematic and if you have a rather large circuit my suggestion is not to generate all the components at the same time and use selected from source to generate them one by one.
4) In display window (shortkey:E) change the x and y, major spacing to 0.01 and the x and y snap spacing to 0.005.

5) Turn on the DRD editor (Option=> DRD edit) and put it on Notify. Avoid using enforce because it does not let you do the connections easily.
6) Using check against source will help you a lot and shows you the remained connections and alert the shorted connections. However, it is not as complete as LVS and when you use one block in your layout it just sees the pins of that block and just accept connections to the pin as an accurate connection while it is not necessary to connect exactly to the pin.
7) In order to create pins check, create labels and in option, for layer name use same as pin and for layer purpose use Pin. Make sure that the signal type is correct. It is also possible to generate all the pins at the same time by using update but remember to apply the
mentioned setting.
8) It is important to check the DRC after doing several connections to avoid any big mistake.
9) Never disable anything in the DRC rule check and if the error is due to full chip criteria just ignore it at the time. The errors that can be ignored are as follows:

  • All density errors
  • Floating gate errors
  • Anything related to the chip corners
  • Dummy layers error

10) In order to remove the antenna DRC error for any metal layer, you need to use jumper which means disconnect the wire and some point close to the gate and complete the connection using a higher metal layer.
11) There are two main kinds of LUP (latch-up) error you may get. One is for the transistors that are connected to the pads and the other one is for the transistors within 20 μm form the transistors that are connected to the pad. For both errors, the transistors must be surrounded by a Ring (Shortkey:Shift+G). The NMOS transistor needs a P-ring (P-sub guarding) and the PMOS transistor need an N-ring (N-well guarding). The Ring can be considered like the bulk of the transistors. So for the NMOS it should be connected to the GND and for the PMOS it should be connected to the VDD. For NMOS transistors the error usually goes away just with the ring. For the PMOS transistors that the ring is not enough to remove the error draw an Nwell layer on all of them.

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